Cadence ChipStack Reaches Level-5 Autonomy — AI Compresses 5-Week Chip Verification to Under a Day

What Level-5 Autonomy Means in Chip Design

Borrowed from autonomous vehicle terminology, "Level-5" in chip design means the system can independently execute complex design and verification workflows without step-by-step human prompting. Engineers shift from executing individual tasks to supervising outcomes and guiding intent.

At Level-5, the ChipStack AI Super Agent autonomously handles:

• Specification understanding
• RTL (Register-Transfer Level) code generation
• Verification planning
• Formal verification analysis (Jasper)
• Logic simulation (Xcelium)
• Debug and design convergence

Rather than waiting for each manual prompt, the agent evaluates intermediate results, determines its next actions, and iterates toward closure on its own.

The NVIDIA Stack: Nemotron + OpenShell

ChipStack's Level-5 capability is built on two critical NVIDIA components:

OpenShell is more than a containerized execution environment. It enforces governance policies, provides isolation, and manages access to tools, infrastructure, and design data — protecting sensitive semiconductor IP while enabling autonomous operation. Cadence's physics-based EDA engines combined with OpenShell's security architecture create a practical path from supervised pilots to production-grade autonomous flows.

NVIDIA itself runs billions of compute hours annually to verify chip designs. Engineers at NVIDIA are now using ChipStack agents to run hundreds of dynamic simulations per engineer, replacing manual workflows that previously consumed weeks.

ChipStack Evolution Timeline

From acquisition to Level-5 autonomy in seven months.

Why Verification Is the Bottleneck

Chip verification has historically been one of the most time-consuming phases of semiconductor design. A single RTL verification loop for a complex chip can take five weeks. Multiply that across dozens of design iterations, and the timeline impact is massive.

Altera's formal verification architect Shahid Ikram presented at CadenceLIVE that for small and medium-sized designs, ChipStack achieves approximately 95% automation from time zero — meaning the agent drives nearly the entire verification flow without human prompting from the start. For more complex designs, he recommended combining a decomposition agent with a coverage feedback agent to handle completeness requirements.

Broader Implications for Semiconductor Development

If Level-5 autonomy delivers on its promise at scale, the implications extend beyond individual engineering efficiency. Verification cycles that used to gate tape-out schedules by weeks could be compressed to days. Smaller semiconductor teams could punch above their weight by offloading the most labor-intensive validation work to AI agents. The risk: over-reliance on agent-generated results without adequate engineer oversight — which is exactly why OpenShell's governance layer and the "inspect and guide" collaboration model are built into the architecture from the start.