Introduction: Memory Is the Bottleneck of the AI Era

If you want to understand why AI hardware is so expensive, why NVIDIA's GPUs command the prices they do, and why two South Korean chipmakers are at the center of one of the most strategically important supply chains in the world, you need to understand High Bandwidth Memory — HBM.

The transformer architecture that underpins every large language model is a memory-hungry beast. During training and inference, the model needs to load enormous matrices of weights, intermediate activations, and attention maps at extremely high speed. Standard DRAM — the kind in your laptop — is too slow. Standard GDDR — the kind on gaming GPUs — has enough bandwidth for graphics but not enough for the parallelism and sheer data volume of AI workloads.

HBM solves this problem. It is the reason an NVIDIA H100 can process AI workloads at the scale it does. And in 2026, the competition to produce the best, fastest, most reliable HBM chips is one of the highest-stakes industrial battles in the global semiconductor industry.

At the center of that battle are two companies: Samsung Electronics, the world's largest chipmaker by revenue, and SK Hynix, a formidable rival that in the HBM segment has managed to outmaneuver its larger competitor at a critical moment in history.

What Is HBM? A Technical Foundation

The Problem HBM Solves

Memory bandwidth — the rate at which data can be moved between memory and the processor — is the limiting factor for AI performance. A GPU like the H100 has 80GB of HBM3 memory. If that memory could only communicate at LPDDR5 speeds (around 68 GB/s), the GPU's thousands of compute cores would spend most of their time waiting for data.

HBM solves this through two architectural innovations:

1. Wide I/O Interface: Where standard DRAM uses a 64-bit or 128-bit memory bus, HBM uses a 1,024-bit memory bus per stack. This means vastly more data can flow per clock cycle.

2. 3D Stacking with Through-Silicon Vias (TSVs): Instead of placing memory chips side-by-side on a circuit board (as in traditional DIMM configurations), HBM stacks multiple DRAM dies vertically. Each die is connected to the one below it via thousands of microscopic copper pillars called through-silicon vias, which pass through the silicon itself. This dramatically reduces the distance data travels and increases the number of connections.

The stacked package — typically 8 or 12 DRAM dies plus a base logic die — is then mounted on an interposer alongside the GPU chip. The interposer is a silicon "bridge" that connects the GPU and the HBM stacks with extremely dense, short interconnects, providing massive bandwidth at low power.

The HBM Generations Explained

Generation Bandwidth per Stack Capacity per Stack Key Users Volume Production Start
HBM 128 GB/s Up to 4GB AMD Fiji GPU 2015
HBM2 256 GB/s Up to 8GB NVIDIA V100 2017
HBM2E 460 GB/s Up to 16GB NVIDIA A100 2020
HBM3 665 GB/s Up to 24GB NVIDIA H100 2022
HBM3E 1,280 GB/s Up to 36GB NVIDIA H200, GB200 2024
HBM4 ~2,000+ GB/s (projected) Up to 64GB Next-gen AI accelerators 2025–2026

The leap from HBM2E to HBM3 was significant. The leap from HBM3 to HBM3E was even larger — a near-doubling of bandwidth — and corresponds directly to the H100 to H200 GPU upgrade that NVIDIA pushed aggressively in 2024 to keep pace with AI workload demand growth.

The Two Rivals: Different Strengths, Same Prize

SK Hynix: First to Market, First in Quality

SK Hynix has been the dominant HBM supplier since the HBM3 generation. The company was the exclusive supplier of HBM3 for NVIDIA's H100 at launch, giving it enormous leverage in the AI boom of 2023–2024.

SK Hynix's advantages include:

  • Manufacturing maturity: Its HBM3 and HBM3E production lines have been running longer, resulting in higher yields and fewer defects
  • NVIDIA relationship: A deep, multi-year qualification process with NVIDIA that has resulted in SK Hynix becoming NVIDIA's preferred — and in some periods, exclusive — HBM supplier
  • TSV yield leadership: SK Hynix has consistently demonstrated better yields in the difficult TSV process, which is critical because a single defective TSV in a stack renders the entire stack unusable
  • Advanced packaging integration: Its HBM stacks have been certified for integration with NVIDIA's CoWoS (Chip on Wafer on Substrate) packaging at Taiwan Semiconductor Manufacturing Company (TSMC)

Samsung: Scale, Resources, and a Difficult 2024

Samsung brings different advantages to the competition:

  • Scale: Samsung operates multiple DRAM fabrication facilities globally and has more raw capacity than SK Hynix
  • Integration: Samsung manufactures both memory and logic (foundry), giving it the potential to develop vertically integrated solutions
  • R&D budget: Samsung's overall semiconductor R&D spend is among the largest in the world
  • LPDDR and GDDR crossover expertise: Experience that could inform future HBM architectural decisions

However, Samsung experienced a painful period in 2023–2024. Its HBM3E chips failed NVIDIA's qualification process due to excessive heat generation under load — a problem traced to the company's use of NCF (Non-Conductive Film) in its stacking process rather than the MR-MUF (Mass Reflow Molded Underfill) process used by SK Hynix. MR-MUF provides better thermal conductivity through the stack, which matters enormously when the chips are densely packed into an AI server.

Samsung's struggle to qualify its HBM3E chips for NVIDIA had real consequences: it missed the high-margin H100 ramp cycle and only captured a partial share of H200 supply. This is the primary reason SK Hynix gained such an outsized share of HBM revenue in 2024.

Market Share: Who Controls HBM in 2026

Based on industry estimates from TrendForce, IDC, and analyst reports from Morgan Stanley and Goldman Sachs:

Company HBM Revenue Share (2023) HBM Revenue Share (2024) HBM Revenue Share (Q1 2026 Est.)
SK Hynix 53% 62% 56%
Samsung 38% 25% 34%
Micron 9% 13% 10%

Several things are visible in this data:

  1. SK Hynix's peak dominance came in 2024, when Samsung's qualification issues were most acute
  2. Samsung has clawed back market share through 2025 and into 2026 as its HBM3E quality issues were resolved
  3. Micron, the U.S.-based memory manufacturer, has made modest but real inroads, driven in part by geopolitical pressure from U.S. government customers and allies to diversify away from Korean-only supply

NVIDIA's HBM Requirements: What It Takes to Qualify

NVIDIA is the critical gatekeeper for HBM qualification. Its requirements are exacting, because a single HBM quality failure in a deployed AI server costs an enterprise customer not just the $30,000+ GPU, but potentially weeks of model training time and significant downstream revenue.

NVIDIA's qualification process for HBM includes:

  • Thermal cycling tests: Chips must survive thousands of temperature cycles across the operating range without degradation
  • Bandwidth verification: Each stack must sustain its rated bandwidth under sustained load
  • Error rate measurements: HBM implements error-correcting code (ECC). NVIDIA measures raw error rates and demands they remain below proprietary thresholds
  • Integration testing: The HBM stacks must interface cleanly with NVIDIA's GPU dies in the CoWoS packaging process at TSMC

The H100 contains 5 HBM3 stacks totaling 80GB. The H200 contains 5 HBM3E stacks totaling 141GB. The GB200 NVL72 rack-scale system — NVIDIA's current flagship — contains 72 GB200 GPUs, each with 8 HBM3E stacks, for a total of 13.5TB of HBM3E in a single rack.

HBM in NVIDIA's 2024–2026 Product Line

GPU HBM Type Total HBM Bandwidth Primary Use Case
A100 HBM2E 80GB 2 TB/s LLM training (prior gen)
H100 SXM HBM3 80GB 3.35 TB/s LLM training and inference
H200 SXM HBM3E 141GB 4.8 TB/s Large model inference, MoE
GB200 HBM3E 192GB 8 TB/s Frontier model training
B300 (est.) HBM4 288GB+ 14+ TB/s Next-gen frontier models

Samsung's HBM3E Quality Problem: What Went Wrong and What Fixed It

Samsung's qualification failure for NVIDIA HBM3E in 2023 has been widely reported but often mischaracterized. The issue was not that Samsung's chips were fundamentally flawed — they met all the baseline electrical specifications. The problem was thermal performance in sustained operation at high power density.

The Root Cause: Bonding Process

The critical difference was in the die-to-die bonding material used during stacking:

  • SK Hynix's approach (MR-MUF): Mass Reflow Molded Underfill fills the gaps between dies with a thermally conductive compound, creating good heat paths throughout the stack
  • Samsung's approach (NCF): Non-Conductive Film creates the inter-die connections but is less thermally conductive than MR-MUF

In the power-dense environment of an AI server, this thermal difference manifested as higher operating temperatures in Samsung's stacks, which in turn caused subtle performance degradation and elevated error rates under sustained workloads.

The Resolution

Samsung invested heavily in transitioning its HBM production lines to MR-MUF bonding through 2024. By Q3 2024, the company had completed qualification of its reformulated HBM3E for select customers, and by Q1 2025, it had received conditional qualification for NVIDIA's supply chain.

Samsung also made structural changes:

  • Established a dedicated HBM quality organization with direct reporting to the Memory Business Division president
  • Increased testing and burn-in procedures before shipment
  • Invested in additional CoWoS-compatible packaging infrastructure

By the end of 2025, Samsung had recovered enough to become a second qualified HBM3E supplier for NVIDIA, though SK Hynix retained the larger share of the H200 and GB200 supply.

The Broader Impact: AI Boom Reshapes the Memory Semiconductor Market

The AI-driven demand surge for HBM has had profound effects on the entire memory semiconductor industry.

Price Dynamics

HBM commands a massive premium over standard DRAM:

  • Standard DRAM (DDR5): approximately $5–8 per gigabyte at commodity pricing
  • HBM3E: approximately $20–30 per gigabyte at market pricing

This premium is sustainable because HBM production is far more complex (more process steps, lower yields, more expensive substrates) and demand is growing faster than capacity.

Capacity Constraints

The global HBM supply is structurally constrained by several factors:

  1. TSMC CoWoS capacity: HBM stacks must be assembled into GPU packages at TSMC, whose CoWoS capacity has been the physical bottleneck since 2023
  2. TSV equipment: The specialized equipment for drilling and filling through-silicon vias has long lead times
  3. Trained engineering talent: HBM packaging engineering is a highly specialized field with a limited global talent pool

These constraints mean that even as Samsung, SK Hynix, and Micron all expand HBM capacity aggressively, demand will remain tight through at least 2027.

Revenue Impact

The shift toward HBM has transformed the economics of the memory industry:

  • SK Hynix's operating profit margin hit 45% in 2024, compared to a near-zero margin during the memory downturn of 2022–2023
  • Samsung's Memory Division, despite its HBM setbacks, still generated record operating profit in 2024 on the strength of standard DRAM price recovery
  • Micron's stock price increased more than 300% from its 2022 trough to its 2024 peak, driven largely by HBM enthusiasm

HBM4: The Next Frontier

Both Samsung and SK Hynix are racing to establish leadership in HBM4, the next generation of the standard, which is expected to reach volume production in 2026.

HBM4 Technical Specifications (Projected)

Specification HBM3E HBM4 (Projected)
Bandwidth per stack 1,280 GB/s 2,000–2,400 GB/s
Capacity per stack Up to 36GB Up to 64GB
I/O width 1,024-bit 2,048-bit (2-high die)
Die stacking 8–12 dies 12–16 dies
Node ~1Znm ~1ynm or smaller
Power efficiency Baseline 20–30% improvement targeted

HBM4 and the Logic Die Innovation

The most significant architectural change in HBM4 is the logic base die. In earlier HBM generations, the logic die was a relatively simple interface chip. In HBM4, the logic die becomes more sophisticated — essentially a small compute chip that can perform memory management, error correction, and data compression locally, reducing the burden on the GPU and the interposer bandwidth.

Both Samsung and SK Hynix are developing custom logic base dies for HBM4, and there is speculation that GPU vendors (primarily NVIDIA and AMD) may specify proprietary logic die designs to differentiate their products.

SK Hynix announced volume production readiness for HBM4 in late 2025, with qualification for the next-generation NVIDIA B300 GPU series proceeding through Q1 2026. Samsung, not wanting to repeat its HBM3E experience, has taken a more cautious approach to HBM4 qualification — prioritizing reliability over time-to-market.

Micron has also announced an HBM4 program, though its volume timeline trails both Korean competitors by 6–9 months.

Geopolitical Dimensions: HBM in the U.S.-China Tech War

No discussion of HBM in 2026 is complete without addressing geopolitics. The U.S. government's export controls on advanced semiconductors to China have created complex dynamics for HBM:

  • NVIDIA's China-specific GPU products (H20, L20) use reduced-specification HBM to remain within export control limits, creating demand for a "second-tier" HBM market
  • South Korea's position as the dominant HBM supplier has increased U.S. attention to the security of the South Korean semiconductor supply chain
  • China's domestic memory efforts — primarily through CXMT (ChangXin Memory Technologies) — are years behind in HBM capability; CXMT is at early HBM2E-equivalent development
  • The U.S. CHIPS Act has included provisions intended to support Micron's HBM expansion as a domestic alternative, though Micron's HBM capacity will remain a minority share through 2027

2026 Outlook: Supply, Demand, and Competition

Demand Drivers

AI infrastructure buildout shows no signs of slowing. Major cloud providers (AWS, Azure, Google Cloud) are each committing to multi-billion dollar AI datacenter expansion programs. The emergence of reasoning models (o3, R2, DeepSeek R3 equivalent) that require more compute per token is actually increasing, not decreasing, the per-chip HBM requirement.

Enterprise AI adoption — companies building private models, fine-tuned vertical AI systems, and inference-heavy applications — is adding a second major demand vector beyond hyperscalers.

Supply Expansion

All three major HBM suppliers are executing aggressive capacity expansion:

  • SK Hynix is building a new HBM-dedicated fab in Yongin, South Korea
  • Samsung has allocated a significant portion of its Pyeongtaek complex to HBM production
  • Micron is expanding HBM capacity at its Singapore and Idaho facilities with CHIPS Act support

Despite this expansion, TrendForce projects that HBM demand will exceed supply through at least 2027, maintaining pricing power for all three manufacturers.

The Competitive Prognosis

Samsung's recovery in HBM3E, combined with its aggressive HBM4 investment, makes it the most important variable in the 2026–2027 competitive landscape. If Samsung can establish quality parity with SK Hynix in HBM4 — and avoid a repeat of the thermal qualification failure — the market will become genuinely competitive for the first time since HBM3.

SK Hynix's challenge is to maintain its technological lead while scaling production. The company has the quality reputation and the NVIDIA relationship, but Samsung's sheer manufacturing scale means that any sustained quality gap closure could rapidly translate into market share recovery.

Conclusion: The Memory War Is the AI War

The competition between Samsung and SK Hynix in HBM is not a niche semiconductor industry story. It is a defining element of the global AI race. The availability, quality, and price of HBM determines how fast AI hardware can advance, how much AI infrastructure costs, and ultimately how quickly AI capabilities can be deployed in the real world.

For investors, HBM is one of the highest-conviction structural trends in semiconductors — a market growing at 40%+ annually, with high barriers to entry, three qualified suppliers globally, and demand driven by one of the most durable technology investment themes in decades.

For technologists, understanding HBM means understanding why memory architecture is a first-class concern in AI system design — not an afterthought. The choice of GPU, the number of HBM stacks, the bandwidth available to the model — these are not marketing numbers. They determine what AI workloads are feasible and what are not.

The memory war is real, it is consequential, and in 2026, it is far from over.